Power metal-oxide-semiconductor field-effect transistors (MOSFETs) are used in power electronic circuits as high frequency switches where they alternate between the on- and off-states. This enables the control of high load power with minimal dissipation in the device. While the power MOSFET is capable of switching at high speeds due to the absence of minority carrier transport, input capacitance limits its performance. In conventional LDMOS and EDMOS transistors, the input capacitance is relatively large due to the large gate area and the large overlap between gate and drain regions that serve as a field plate. Consequently, the upper cutoff frequency is usually limited by the charging and discharging of this input capacitance.
In addition to the gate-to-source capacitance (CGS), a significant gate-to-drain capacitance (CGD) must be included in the analysis due to the overlap of the gate electrode over the drift region.
The total input capacitance CISS is:CISS=CGS+CGD 
If the input capacitance is relatively high, a relatively high gate current is needed to operate power MOSFETs. As a result, the gate switching loss will be significant, especially at switching frequencies beyond 1 MHz. This is not in reference to the gate circuit, it only considers the power loss within the device; a large CGD will result in a large switching loss. CGS is determined by the channel length, L and width, W required to achieve a certain on-resistance. It is optimized in embodiments of this application.
Furthermore, the frequency response limited by the RC charging time constant of the input gate circuit is given by:
      f    INPUT    =      1          2      ⁢      π      ⁢                          ⁢              C        ISS            ⁢              R        G            
Devices with a small CGD will have low switching loss and high cut off frequency.
What is needed, therefore, is a device exhibiting a low CGD employing fabrication techniques compatible with standard CMOS processing.